CMOS output buffer circuit

ABSTRACT

A CMOS output buffer circuit comprises an input unit, a compensation control unit, a first switching unit and a second switching unit. The input unit outputs a data signal in response to a stop signal for determining transmission of the data signal. The compensation control unit determines a power voltage level with reference to the stop signal and the data signal when the data signal is transmitted, and outputs a plurality of compensating signals depending on the power voltage level. The first switching unit including a driving unit driven by the data signal outputted from the input unit and a compensation driving unit driven by combination of the data signal and the plurality of compensating signals compensates change of the power voltage level to output current. The second switching unit operated complementarily with the first switching unit outputs current. Accordingly, the CMOS output buffer circuit supplies a predetermined output current regardless change of a power voltage, thereby reducing power consumption and minimizing overshoot/undershoot noise to stabilize a power supplied to a device.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a CMOS output buffer unit,and more specifically, to a technology of providing a predeterminedoutput current regardless of change of a power voltage, therebystabilizing power.

2. Description of the Prior Art

Generally, a Complementary Metal Oxide Semiconductor (hereinafter,referred to as “CMOS”) output buffer circuit comprises a plurality ofCMOS transistors connected in parallel each including a P-channel MetalOxide Semiconductor (hereinafter, referred to as “PMOS”) Transistor anda N-channel Metal Oxide Semiconductor (hereinafter, referred to as“NMOS”) Transistor.

FIG. 1 is a circuit diagram of a conventional CMOS output buffercircuit.

The conventional CMOS output buffer circuit comprises an inverter IN1, aNAND gate NAND1, a buffer BUF1, a PMOS transistor PM1 and a NMOStransistor NM1.

The NAND gate NAND1 outputs a high level signal regardless of a level ofa data signal DATA if a stop signal STOP is at a high level. The bufferBUF1 buffers the high level signal outputted from the NAND gate NAND1,and the NMOS transistor NM1 driven by an output signal from the bufferBUF1 outputs an output signal OUT having a low level.

Meanwhile, the CMOS output buffer circuit outputs the output signal OUTin response to the data signal DATA if the stop signal STOP is at a lowlevel. If the data signal DATA is at a high level, the PMOS transistorPM1 is driven and the CMOS output buffer circuit outputs the outputsignal OUT having a high level. If the data signal DATA is at a lowlevel, the NMOS transistor NM1 is driven and the CMOS output buffercircuit outputs the output signal OUT at a low level.

In the above-described conventional CMOS output buffer circuit, if apower voltage VDD increases, current flowing through the PMOS transistorPM1 dramatically increases. As a result, the output current becomestemporarily unstable depending on toggling of the data signal DATA.

FIG. 2 is a timing diagram of a conventional CMOS output buffer circuit.

As shown in FIG. 2, in an interval where the stop signal STOP is at alow level and the data signal DATA is normally outputted, the change(ranging from 22 mA to 66 mA) of the current driving ability of outputsignal OUT from the CMOS output buffer circuit depending on change ofthe power voltage VDD is shown to be large.

If the output signal OUT having unstable current driving ability of isused as base current of a NPN-bipolar transistor, the change amount ofcollector current which is output current of the amplified NPN-bipolartransistor becomes larger.

Furthermore, the semiconductor memory device using the large changeamount of output current has unstable power and causes mis-operations.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to preventmis-operations of a semiconductor memory device by providing apredetermined output current regardless of change of a power voltage tosupply a stable power to the semiconductor memory device.

In an embodiment, a CMOS output buffer circuit comprises an input unit,a compensation control unit, a first switching unit and a secondswitching unit. The input unit outputs a data signal in response to astop signal for determining transmission of the data signal. Thecompensation control unit determines a power voltage level withreference to the stop signal and the data signal when the data signal istransmitted, and for outputs a plurality of compensating signalsdepending on the power voltage level. The first switching unit includinga driving unit driven by the data signal outputted from the input unitand a compensation driving unit driven by combination of the data signaland the plurality of compensating signals to compensates change of thepower voltage level to output current. The second switching unitoperated complementarily with the first switching unit outputs current.

BRIEF DESCRIPTION OF THE DRAWINGS

Other aspects and advantages of the present invention will becomeapparent upon reading the following detailed description and uponreference to the drawings in which:

FIG. 1 is a circuit diagram of a conventional CMOS output buffercircuit;

FIG. 2 is a timing diagram of a conventional CMOS output buffer circuit;

FIG. 3 is a circuit diagram of a CMOS output buffer circuit according toan embodiment of the present invention;

FIG. 4 is a diagram of a power voltage level detecting unit of FIG. 3;

FIG. 5 is a circuit diagram of a sub-power level detector of FIG. 4; and

FIG. 6 is a timing diagram of a CMOS output buffer circuit according toan embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described in detail with reference to theaccompanying drawings.

FIG. 3 is a circuit diagram of a CMOS output buffer circuit according toan embodiment of the present invention.

In an embodiment, the CMOS output buffer circuit comprises an input unit10, a compensation control unit 20, a first switching unit 30 and asecond switching unit 40.

The input unit 10 comprises an inverter IN2, a NAND gate NAND2 and abuffer BUF2.

The inverter IN2 inverts a stop signal STOP, and the NAND gate NAND2performs a NAND operation on an output signal from the inverter IN2 anda data signal DATA. The buffer BUF2 buffers an output signal from theNAND gate NAND2.

The compensation control unit 20 comprises an OR gate OR1, buffers BUF3and BUF4, an inverter IN3 and a power voltage level detecting unit 200.

The OR gate OR1 performs an OR operation on the stop signal STOP and thedata signal DATA. The buffers BUF3 and BUF4 connected in parallel bufferan output signal from the OR gate OR1, respectively. The inverter IN3inverts the output signal from the OR gate OR, and outputs the invertssignal to the power voltage level detecting unit 200.

The power voltage level detecting unit 200 is disabled if the stopsignal STOP is at a high level, and enabled if the stop signal STOP isat a low level.

If the stop signal STOP is at the low level, and the data signal DATA isat a low level, the buffer BUF3 outputs a low level signal to an enableterminal ENB to enable the power voltage level detecting unit 200, andthe inverter IN3 outputs a high level signal to a clock terminal CKB.The power voltage level detecting unit 200 detects and latches the powervoltage level synchronously with respect to the clock terminal CKB.

Thereafter, if the data signal DATA having the low level transits to ahigh level, the power voltage level detecting unit 200 outputscompensating signals A1˜A5 to the first switching unit 30.

The first switching unit 30 comprises a driving unit 31 and a pluralityof compensation driving units 32˜36.

The driving unit 31 and the compensation driving units 32˜36 comprise ORgates OR2˜OR7, buffers BUF5˜BUF10 and PMOS transistors PM2˜PM7.

The driving unit 31 is driven by an output signal from the input unit10, and the compensation driving units 32˜36 are driven by combinationof the output signal from the input unit 10 and the compensating signalsA1˜A5 outputted from the power voltage level detecting unit 200.

The driving unit 31 comprises the OR gate OR2, the buffer BUF5 and thePMOS transistor PM2. The OR gate OR2 performs an OR operation on theoutput signal from the input unit10. The buffer BUF5 buffers an outputsignal from the OR gate OR2. The PMOS transistor PM2 outputs a powervoltage VDD level depending on an output signal from the buffer BUF5.

The above-described driving unit 31 is constantly driven if the stopsignal STOP is at the low level and the data signal DATA is at the highlevel. The compensation driving units 32˜36 have the same structure asthat of the driving unit 31 except that they are driven depending onchange of the power voltage level.

For example, if the power voltage level is over 5.5V, only the drivingunit 31 is driven. If the power voltage level ranges from 5.0V˜5.5V, thedriving unit 31 and the compensation driving unit 32 are driven. If thepower voltage ranges from 4.5V-5.0V, the driving unit 31 and thecompensation driving units 32 and 33 are driven. If the power voltageranges from 4.0V˜4.5V, the driving unit 31 and the compensation drivingunits 32˜34 are driven. If the power voltage ranges from 3.5V˜4.0V, thedriving unit 31 and the compensation driving units 32˜35 are driven. Ifthe power voltage ranges from 3.0V˜3.5V, the driving unit 31 and thecompensation driving units 32˜36 are driven.

The second switching unit 40 is a NMOS transistor NM2 having a drainconnected to the driving unit 31 and the plurality of compensationdriving units 32˜36 and a source to receive a ground voltage. The NMOStransistor NM2 outputs a ground voltage VSS level depending on an outputsignal from the buffer BUF5.

The second switching unit 40 is constantly driven regardless of the datasignal DATA when the stop signal STOP is at the high level, and outputsan output signal OUT having a low level. If the stop signal STOP becomesat the low level, the second switching unit 40 is driven when the datasignal DATA is at the low level.

In this way, the CMOS output buffer circuit according to an embodimentof the present invention comprises a plurality of PMOS transistorsPM2˜PM7 for driving large current which are connected in parallel. Here,one PMOS transistor PM2 is the base, and the rest PMOS transistorsPM3˜PM7 are turned on depending on change of the power voltage level. Asa result, the CMOS output buffer circuit outputs output current having apredetermined level regardless of change of the power voltage level.

FIG. 4 is a diagram of the power voltage level detecting unit 200 ofFIG. 3.

The power voltage level detecting unit 200 comprises a plurality ofsub-power level detectors (hereinafter, referred to as “PLD”) 201˜205and a plurality of latch units 206˜210.

The plurality of PLDs 201˜205, which are enabled if the data signal DATAbecomes at the low level, detect a level of the power voltage, andoutputs detecting signals DET1˜DET5 depending on the detected level ofthe power voltage.

The PLD 201 outputs the detecting signal DET1 when the detected powervoltage ranges from 5.0V˜5.5V. The PLD 202 outputs the detecting signalDET2 when the detected power voltage ranges from 4.5V˜5.0V. The PLD 203outputs the detecting signal DET3 when the detected power voltage rangesfrom 4.0V˜4.5V. The PLD 204 outputs the detecting signal DET4 when thedetected power voltage ranges from 3.5V˜4.0V. The PLD 205 outputs thedetecting signal DET5 when the detected power voltage ranges from3.0V˜3.5V.

The latch units 206˜210 latch the detecting signals DET1˜DET5,respectively, and then output the compensating signals A1˜A5 in responseto signals applied to clock terminals CK and CKB if the data signal DATAbecomes at the high level.

FIG. 5 is a circuit diagram of one of the sub-power level detectors201˜205 of FIG. 4.

Each of the PLDs 201˜205 comprises a PMOS transistor PM8, resistors R1and R2, a NMOS transistor NM3 and an inverter IN4.

The PMOS transistor PM8 is controlled by a signal inputted to the enableterminal ENB, and has a source to receive the power voltage VDD and adrain connected to one side of the resistor R1.

The resistors R1 and R2 are connected serially. One side of the resistorR1 is connected to the drain of the PMOS transistor PM8, and one side ofthe resistor R2 is connected to a drain of the NMOS transistor NM3.

The NMOS transistor NM3 has a source to receive a ground voltage, and agate and a drain which are connected each other. The inverter IN4 isconnected to the common node of the resistors R1 and R2.

The PMOS transistor PM8 is turned on when the stop signal STOP and thedata signal DATA are at the low level, and turned off when the stopsignal STOP is at the low level and the data signal DATA is at the highlevel.

Here, an output signal from the inverter IN4 becomes at a high level ifthe power voltage VDD is higher than a reference voltage, and at a lowlevel if the power voltage VDD is lower than the reference voltage. Forexample, in case of the PLD 201, when the reference voltage is 5.5V, thedetecting signal DET1 becomes at a high level if the power voltage VDDis over 5.5V, and at a low level if the power voltage VDD is below 5.5V.

In the above-described PLDs 201˜205, values of the reference voltage areregulated depending on the detected power voltage and the ratio of theresistors R1 and R2. As a result, the PLD can be embodied depending onthe level change of the power voltage by regulating values of theresistors R1 and R2 and a width and length W/L of the NMOS transistorNM3.

FIG. 6 is a timing diagram of a CMOS output buffer circuit according toan embodiment of the present invention.

In an embodiment, the CMOS output buffer circuit constantly turns on theNMOS transistor NM2 and turns off the PMOS transistors PM2˜PM7regardless of the level of the data signal DATA if the stop signal STOPis at the high level. Also, the CMOS output buffer circuit disables thepower voltage level detecting unit 200, thereby removing stand-bycurrent.

The CMOS output buffer circuit controls the operations of the PMOStransistors PM2˜PM7 and the NMOS transistor NM2 depending on the levelof the data signal DATA if the stop signal STOP becomes at the lowlevel.

More specifically, if the stop signal STOP and the data signal DATA areat the low level, a node N1 becomes at a high level and a node N2 alsobecomes at a high level. As a result, the PMOS transistor PM2 is turnedoff and the NMOS transistor NM2 is turned on so that the CMOS outputbuffer circuit outputs the output signal OUT having a low level. Here,the power voltage level detecting unit 200 is enabled, detects the levelof the power voltage VDD, latches the detecting signals DET1˜DET5depending on the power voltage level, and outputs the compensatingsignals A1˜A5 depending on the detected level of the power voltagelevel.

Here, the detecting signals DET1˜DET5 depend on the detection basis ofthe power voltage level, for example, ranging from 5.0V to 5.5V, from4.5V to 5.0V, from 4.0V to 4.5V, from 3.5V to 4.0V and from 3.0V to3.5V, respectively. The detection level can be more subdivided by auser.

Meanwhile, if the stop signal STOP becomes at the low level and the datasignal DATA becomes at the high level, the nodes N1 and N2 become at alow level, and the PMOS transistor PM2 is turned on. Additionally, thepower voltage level detecting unit 200 outputs the compensating signalsA1˜A5 in response to the detecting signals DET1˜DET5 latched by thedetected level of the power voltage VDD.

When the power voltage level is over 5.5V, the compensating signalsA1˜A5 become all at a high level, and the PMOS transistors PM3˜PM7 areturned off. As a result, only the PMOS transistor PM2 is driven. Whenthe power voltage level ranges from 5.0V˜5.5V, only the compensatingsignal A1 becomes at a low level, and the PMOS transistors PM2 and PM3are driven. When the power voltage level ranges from 4.5V˜5.0V, thecompensating signals A1 and A2 become at the low level, and the PMOStransistors PM2˜PM4 are driven. When the power voltage level ranges from4.0V˜4.5V, the compensating signals A1˜A3 become at the low level, andthe PMOS transistors PM2˜PM5 are driven. When the power voltage levelranges from 3.5V˜4.0V, the compensating signals A1˜A4 become at the lowlevel, and the PMOS transistors PM2˜PM6 are driven. When the powervoltage level ranges from 3.0V˜3.5V, the compensating signals A1˜A5become at the low level, and the PMOS transistors PM2˜PM7 are driven. Asa result, the CMOS output buffer circuit outputs the output signal OUTat the high level.

Table 1 shows the above-described operation of the CMOS output buffercircuit. TABLE 1 Power Number of voltage driven VDD (V) N1 = N2 N3 N4 N5N6 N7 PMOS 5.7 L H H H H H 1 5.3 L L H H H H 2 4.7 L L L H H H 3 4.3 L LL L H H 4 3.7 L L L L L H 5 3.3 L L L L L L 6

In this way, the power voltage level detecting unit 200 outputs thecompensating signals A1˜A5 depending on the detected level of the powervoltage, and switches the PMOS transistors PM3˜PM7 of the compensationdriving units 32˜36 in response to the compensating signals A1˜A5. As aresult, the number of turned-on PMOS transistors increases or decreasesin inverse proportion to the power voltage level.

As shown in FIG. 6, since the compensation driving unit is operateddepending on the level of the power voltage VDD, the change amount ofthe output signal OUT becomes smaller ranging from 19 mA to 31 mA.

As discussed earlier, a CMOS output buffer circuit according to anembodiment of the present invention supplies a predetermined outputcurrent regardless change of a power voltage, thereby reducing powerconsumption and minimizing overshoot/undershoot noise to stabilize apower supplied to a device.

While the invention is susceptible to various modifications andalternative forms, specific embodiments have been shown by way ofexample in the drawings and described in detail herein. However, itshould be understood that the invention is not limited to the particularforms disclosed. Rather, the invention covers all modifications,equivalents, and alternatives falling within the spirit and scope of theinvention as defined in the appended claims.

1. A CMOS output buffer circuit comprising: an input unit for outputtinga data signal in response to a stop signal for determining transmissionof the data signal; a compensation control unit for determining a powervoltage level with reference to the stop signal and the data signal whenthe data signal is transmitted and for outputting a plurality ofcompensating signals depending on the power voltage level; a firstswitching unit including a driving unit driven by the data signaloutputted from the input unit and a compensation driving unit driven bycombination of the data signal and the plurality of compensating signalsto compensate change of the power voltage level to output current; and asecond switching unit operated complementarily with the first switchingunit and for outputting current.
 2. The circuit according to claim 1,wherein the compensation control unit comprises: a logic operation unitfor performing a logic operation on the stop signal and the data signal;a plurality of buffers for buffering an output signal from the logicoperation unit; an inverting unit for inverting an output signal fromthe logic operation unit; and a power voltage level detecting unitenabled by an output signal from the buffer if the data signal is at alow level, to detect and latch the power voltage level by using anoutput signal from the inverting unit as a clock and to output theplurality of compensating signals if the data signal becomes at a highlevel.
 3. The circuit according to claim 2, wherein the power voltagelevel detecting unit comprises: a plurality of sub-power level detectorsenabled if the stop signal and the data signal are at a low level, todetect the power voltage level and to output a plurality of detectingsignals depending on the power voltage level; and a plurality of latchunits for latching the plurality of detecting signals and outputting theplurality of compensating signals if the data signal becomes at the highlevel.
 4. The circuit according to claim 3, wherein the sub-power leveldetector comprises: a PMOS transistor having a source connected to apower voltage and controlled by an output signal from the buffer; afirst resistor having one side connected to a drain of the PMOStransistor; a second resistor having one side connected to the otherside of the first resistor; a NMOS transistor having a gate and a drainconnected to the other side of the second resistor, and a source toreceive a ground voltage; and an inverting unit for inverting an outputsignal from the common node of the first resistor and the secondresistor.
 5. The circuit according to claim 4, wherein the sub-powerlevel detector varies the size of the first resistor, the secondresistor and the NMOS transistor, sets a reference voltage, compares thepower voltage with the set reference voltage, and detects the powervoltage level.
 6. The circuit according to claim 1, wherein thecompensation driving unit comprises: a first compensation driving unitswitched by a first compensating signal corresponding to the powervoltage level of 5.0V˜5.5V when the data signal is transmitted; a secondcompensation driving unit switched by a second compensating signalcorresponding to the power voltage level of 4.5V˜5.0V when the datasignal is transmitted; a third compensation driving unit switched by athird compensating signal corresponding to the power voltage level of4.0V˜4.5V when the data signal is transmitted; a fourth compensationdriving unit switched by a fourth compensating signal corresponding tothe power voltage level of 3.5V˜4.0V when the data signal istransmitted; and a fifth compensation driving unit switched by a fifthcompensating signal corresponding to the power voltage level of3.0V˜3.5V when the data signal is transmitted.
 7. The circuit accordingto claim 6, wherein each of the first to the fifth compensation drivingunits comprises: a logic operation unit for performing a logic operationon the first to the fifth compensating signals, respectively; a bufferfor buffering an output signal from the logic operation unit; and a PMOStransistor switched by an output signal from the buffer.
 8. The circuitaccording to claim 1, wherein the driving unit comprises: a logicoperation unit for performing a logic operation on an output signal fromthe input unit; a buffer for buffering an output signal from the logicoperation unit; and a PMOS transistor switched by an output signal fromthe buffer.
 9. The circuit according to claim 1, wherein the secondswitching unit is a NMOS transistor.